A Low-power design of quantization for H.264 video coding standard

Show full item record

Title: A Low-power design of quantization for H.264 video coding standard
Author: Michael, Michael; Hsu, Kenneth
Abstract: Low-power quantization architecture for H.264/AVC is presented and implemented on VLSI. The multiplication operation is replaced with shifts and additions. Similar designs were proposed which had 75.2% area and 76.30/0 power on average saved compared with original H.264 quantization scheme, along with an error percent within 6.4% range. In this paper, the improved architecture has error percent within 2.4% range. The power and area saved on average is -8% compared to designs of similar architecture.
Record URI: http://hdl.handle.net/1850/10130
Date: 2008

Files in this item

Files Size Format View
KHsuConfProc09-2008.pdf 985.0Kb PDF View/Open

The following license files are associated with this item:

This item appears in the following Collection(s)

Show full item record

Search RIT DML


Advanced Search

Browse