Capacity and productivity modeling for research laboratories using a representative product load

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dc.contributor.author Kuhl, Michael
dc.contributor.author Ramamurthl, Vikram
dc.contributor.author Hirschman, Karl
dc.contributor.author Laubisch, Gregory
dc.date.accessioned 2009-07-23T20:01:47Z
dc.date.available 2009-07-23T20:01:47Z
dc.date.issued 2004-05
dc.identifier.citation In the Proceedings of the 2004 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, Piscataway, New Jersey, pp. 157-161, May 2004 en_US
dc.identifier.uri http://hdl.handle.net/1850/10250
dc.description.abstract Efficient use of R&D laboratory resources including fabrication and metrology tools, analytical equipment, and operators and technicians is critical to product development, time to market, and ultimately company success. Capacity and productivity modeling in R&D fabs presents significant challenges and is not usually well understood. Simulation modeling can provide an accurate representation of the R&D fab that can be used to investigate the operational aspects of the fab and provide a quantitative statistical analysis of Jab performance measures. A simulation study of the Semiconductor & Microsystems Fabrication Laboratory (SMFL) al the Rochester Institute of Technology (RlT) is used to present a case study on this methodology. A baseline CMOS process is used as the representative product load, which accounts for the variety of research activities in progress in the SMFL. The fab performance is assessed by the cycle time, WIP, and throughput of representative load lots. en_US
dc.language.iso en_US en_US
dc.publisher Institute of Electrical and Electronics Engineers en_US
dc.title Capacity and productivity modeling for research laboratories using a representative product load en_US
dc.type Proceedings en_US

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