Design, fabrication and implementation of a hash table processor

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Title: Design, fabrication and implementation of a hash table processor
Author: Ketrick, Robert Paul
Abstract: Hash tables have been used frequently to implement organized data table storage. However, there is a great deal of overhead in executing the hash algorithm every time the table is accessed. Alternatively, a content addressable memory (CAM) is a hardware implementation of an organized data table. A CAM requires very complex hardware design for each memory cell and therefore yeilds a very low cell density on each chip. This requires a large number of expensive chips to implement a large hash table. In this thesis a simple hash function was designed into an integrated circuit using 4- micron NMOS technology. The scope of this thesis covers theoretical development, circuit design, simulation and fabrication. This chip performs a simple hashing algorithm using standard RAM to store the data and can interface to several 8-bit and 16-bit microprocessors. The design of this device is aimed at improving the speed of compilers, assemblers, and whenever fast access to organized data tables are needed.
Record URI: http://hdl.handle.net/1850/10497
Date: 1987

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