A Test chip approach to routine process control

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dc.contributor.advisor Fuller, Lynn
dc.contributor.advisor Turkman, R.
dc.contributor.advisor Ramanan, S.
dc.contributor.author Meisenzahl, Eric J.
dc.date.accessioned 2009-09-21T12:51:17Z
dc.date.available 2009-09-21T12:51:17Z
dc.date.issued 1988-03
dc.identifier.uri http://hdl.handle.net/1850/10562
dc.description.abstract A procedure for determining process control and yield prediction is presented which primarily serves to evaluate the quality and repeatability of critical fabrication steps, but also serves to quantify process capabilities and limitations for future design considerations. This can be accomplished through the use of a specially designed test chip. The test chip is designed for use in determining the process control and fabrication capability of the Microelectronic Engineering Department's fabrication lab of Rochester Institute of Technology. en_US
dc.language.iso en_US en_US
dc.relation RIT Scholars content from RIT Digital Media Library has moved from http://ritdml.rit.edu/handle/1850/10562 to RIT Scholar Works http://scholarworks.rit.edu/theses/5564, please update your feeds & links!
dc.subject Process control en_US
dc.subject Integrated circuits en_US
dc.subject Test chips en_US
dc.subject.lcc TS156.8.M43 1988
dc.subject.lcsh Process control--Technological innovations--Testing en_US
dc.subject.lcsh ntegrated circuits--Design and construction en_US
dc.title A Test chip approach to routine process control en_US
dc.type Thesis en_US
dc.description.college Kate Gleason College of Engineering en_US
dc.description.department Department of Electrical Engineering en_US

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