Leveraging firmware in multichip systems to maximize FPGA resources: An Application of self-partial reconfiguration

Show full item record

Title: Leveraging firmware in multichip systems to maximize FPGA resources: An Application of self-partial reconfiguration
Author: Galindo, Juan; Peskin, Eric; Larson, Brad; Roylance, Gene
Abstract: A number of SRAM-based field programmable gate arrays (FPGAs) allow for partial reconfiguration (PR). Partial reconfiguration can be used to maximize the resource utilization in these FPGAs. Current methodologies use both external and self partial reconfiguration for this purpose. On mature multichip (MC) systems that have not made use of the PR features of their SRAM-based FPGA(s), however, these methodologies would require changes in the existing FPGA configuration protocol and/or associated hardware outside the array. This paper presents a novel methodology that makes PR features available to these systems for the purpose of maximizing their FPGA resources without the modifications required by the current methodologies. The proposed methodology reuses an existing data interface to send the PR data to the array and directs this data to the FPGA’s internal configuration port. A prototype of this methodology is demonstrated on a commercial color space conversion (CSC) engine design using two Xilinx Virtex-II Pro FPGAs.
Record URI: http://hdl.handle.net/1850/10564
Date: 2008

Files in this item

Files Size Format View
EPeskinConfProc2008.pdf 209.7Kb PDF View/Open

The following license files are associated with this item:

This item appears in the following Collection(s)

Show full item record

Search RIT DML


Advanced Search

Browse