Development and modeling of a low temperature thin-film CMOS on glass

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Title: Development and modeling of a low temperature thin-film CMOS on glass
Author: Manley, Robert G.
Abstract: The push to develop integrated systems using thin-film transistors (TFT) on insulating substrates (i.e. glass) has always been limited due to low-mobility semiconducting films such as amorphous and polycrystalline silicon. Corning Incorporated is developing a new substrate material known as silicon-on-glass (SiOG). It is intrinsically better than amorphous and polycrystalline silicon materials due to its single crystal nature of the silicon film. This however does not mitigate the challenges associated with low temperature CMOS process and fabrication. The first generation of TFTs fabricated at RIT showed the potential of SiOG as a viable substrate material, but were plagued by considerable short comings such as high leakage and low transconductance. As part of this study, refinements to TFT processing on SiOG have demonstrated significant improvement to TFT performance and uniformity, showing increase transconductanace/mobility, lower subthreshold swing, tighter VT distributions, and near symmetrical NFET and PFET operation about 0 V. With these improvements minimal steps have been added to the manufacturing process, keeping simple and adoptable by the flat panel display (FPD) industry. Device modeling clearly demonstrates the key areas important to electrical operation, such as dopant activation, interface charge/trap reduction, and workfunction engineering. It addition, modeling and simulation have helped to explain the governing physics of device operation explaining non-ideal effects such as gate induced drain leakage (GIDL) and various mobility degradation mechanism. An overview of device design, process refinements and device operation is presented. Process modifications and resulting benefits are discussed along with CMOS integration on SiOG.
Record URI: http://hdl.handle.net/1850/11202
Date: 2009-02-06

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