The RIT IEEE-488 buffer design

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Title: The RIT IEEE-488 buffer design
Author: Connor, John
Abstract: This document describes the design of an NMOS ASIC used to control an RIT IEEE-488 Buffer previously designed by the author. Past designs used discrete components to implement an asynchronous controller and a synchronous, one-hot controller. The present design utilizes a multiple controller architecture incorporated within the ASIC. The ASIC is used to control bus protocol, bus transceivers, and memory. At power-up, the buffer configures itself as an active listener on the bus and waits for a talker to initiate communication. The buffer accepts a data file (a plot file for example) from the talker, then takes control of the bus, addresses a listener, transfers the stored data to the listener, unaddresses the listener, releases the bus, and finally, reassumes the active listener configuration. The RIT IEEE-488 buffer can realize time savings for a user in a controllerless system. The buffer accepts data from a talker in a matter of seconds and then takes on the chore of driving a slow listener. Thus, the talker is returned quickly to the operator for further use. At present, the buffer isn't queueable - it cannot accept another data file until it completes the transfer of the present file. The author has also added five nmos cells (schematic/layout) into the '/user/pub' directory on the Apollo workstations in the Computer Engineering Department's VLSI LAB at RIT. Cell names are VSCLK, SYNC, CLOCK_GEN_STACK, PAD_TRISTATE, and PAD_TRISTATE_BUFFERED. All five cells have been simulated and successfully run through DRC, ERC, and LVS checks.
Record URI: http://hdl.handle.net/1850/11259
Date: 1992-02

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