N-Well CMOS process integration

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dc.contributor.advisor Fuller, Lynn
dc.contributor.advisor Pearson, Robert
dc.contributor.author Price, David T.
dc.date.accessioned 2010-01-29T19:30:51Z
dc.date.available 2010-01-29T19:30:51Z
dc.date.issued 1992-11
dc.identifier.uri http://hdl.handle.net/1850/11261
dc.description.abstract The predominant integrated circuit fabrication technologies used for VLSI devices are CMOS, and BiCMOS. The goal of this work was to develop a CMOS process that could be converted into a BiCMOS technology. For this reason an N-Well CMOS process was selected, and fabricated in the Microelectronic Engineering clean room. This paper reviews the test chip design, process simulation, fabrication, and electrical characterization of this process. The device fabrication was successful, and the electrical testing clearly indicated what measures need to be taken to improve the process. en_US
dc.language.iso en_US en_US
dc.relation RIT Scholars content from RIT Digital Media Library has moved from http://ritdml.rit.edu/handle/1850/11261 to RIT Scholar Works http://scholarworks.rit.edu/theses/5574, please update your feeds & links!
dc.subject Integrated circuits en_US
dc.subject.lcc TK7871.99.M44 P74 1992
dc.subject.lcsh Metal oxide semiconductors, Complementary en_US
dc.title N-Well CMOS process integration en_US
dc.type Thesis en_US
dc.description.college Kate Gleason College of Engineering en_US
dc.description.department Department of Electrical Engineering en_US

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