A Methodology for NMOS VLSI manufacturing: From design to test

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Title: A Methodology for NMOS VLSI manufacturing: From design to test
Author: Chomicz, Thecla
Abstract: The development of a methodology to integrate design automation with the fabrication of very large scale integrated circuits is presented. A multiplier circuit is used as an example of a full custom circuit development, simulation and layout using Apollo workstations. Several other circuits, such as a 16x1 static random access memory (SRAM), a three bit counter, and a stepper motor controller, are included in the final layout. The final layout also includes smaller test circuits such as an AND gate, a shift register and a full adder. The discussion of circuit simulation includes the calculation of SPICE model parameters based on the Rochester Institute of Technology's Microelectronic Engineering Department's NMOS process. The design and use of a standard pad frame cell based on the same fabrication process is also discussed. The final sections discuss fabrication and test of the NMOS devices and circuits using the Microelectronic Engineering Department's undergraduate student factory.
Record URI: http://hdl.handle.net/1850/11314
Date: 1990-09

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