Phosphorus implants for off-state improvement of SOI CMOS fabricated at low temperature

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Title: Phosphorus implants for off-state improvement of SOI CMOS fabricated at low temperature
Author: Singh, Siddhartha
Abstract: A study on the influence of phosphorus implanted source/drain features on the off-state performance of transistors fabricated in thin-film crystalline silicon at low temperature is presented. Complementary Metal Oxide Semiconductor (CMOS) thin film transistors (TFTs) were fabricated on silicon-on-insulator (SOI) substrates; both NFET and PFET devices in the same p-type layer. Lightly Doped Drain (LDD) features were implemented on NFETs, and a surface-halo source barrier (N-barrier) was implemented on PFETs, using a common implant step. A new mask set was designed with fine resolution of gate offset to investigate small changes in placement of the LDD/ N-barrier structures. The focus of this investigation was the off-state characteristics of the devices; the implanted features were designed to help suppress the effects of Gate Induced Drain Leakage (GIDL) and Drain Induced Barrier Lowering (DIBL). Along with the mask design offsets, a number of process variations resulted in TFTs with different degrees of gate overlap and device symmetry. Electrical device characteristics are presented in the study, with comparisons to devices simulated using Silvaco ® Atlas.
Record URI: http://hdl.handle.net/1850/11427
Date: 2009-02

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