VLSI design of a priority arbitrator for shared buffer ATM switches

Show full item record

Title: VLSI design of a priority arbitrator for shared buffer ATM switches
Author: Lin, Yu-Sheng; Yang, Shanchieh; Fang, Su-Jen; Shung, C. Bernard
Abstract: Priority arbitration is an essential part of the ATM switches in order to support the integration of telecommunication services with difference characteristics. Service priority control selects the connection to output a cell among all connections destined to the same output port. Discard priority contral selects the connection to discard a cell when the shared buffer is full. In this paper we present a VLSI design of a priority arbitrator for shared buffer ATM switches. This priority arbitrator is targeted to support our new service priority control scheme, reactive bandwidth arbitration (RBA), and new discard priority control scheme, local pushout discarding (LPD). The priority arbitrator is designed for an 8x8 shared buffer ATM switch with four priority classes per port and a link rate of 622 Mbps. The chip has 130k gates in a chip area of B7.88 mm2 using 0.6 micrometers CMOS technology.
Record URI: http://hdl.handle.net/1850/11552
Date: 1997

Files in this item

Files Size Format View
SYangConfProc1997.pdf 464.5Kb PDF View/Open

The following license files are associated with this item:

This item appears in the following Collection(s)

Show full item record

Search RIT DML


Advanced Search

Browse