The Design and implementation of an 8 bit CMOS microprocessor

Show full item record

Title: The Design and implementation of an 8 bit CMOS microprocessor
Author: Correll, Jeffrey
Abstract: The design and implementation cycle of an 8 bit CMOS microprocessor is discussed. The primary steps in the design procedure of the microprocessor consists of instruction selection, instruction encoding and organizational specification. A simple architecture is chosen to allow the emphasis of this investigation is focused upon the entire design procedure, Software behavioral models of functional blocks within the processor are used to validate the architecture. The functional blocks are then replaced with logic circuit models and tested. After logical simulations of all blocks have been completed, physical simulations of the logic circuits are performed using a SPICE like simulator to extract delay characteristics of longest circuit paths. Using this delay information, a preliminary estimate of processor speed is possible. Layout of the processor is generated using the Department of Computer Engineering's 2 uM CMOS Standard Cell Library.
Record URI: http://hdl.handle.net/1850/11649
Date: 1992-06

Files in this item

Files Size Format View
JCorrellThesis06-1992.pdf 2.922Mb PDF View/Open

The following license files are associated with this item:

This item appears in the following Collection(s)

Show full item record

Search RIT DML


Advanced Search

Browse