Simulation of a morphological image processor using VHDL - Part II: Control Mechanism

Show full item record

Title: Simulation of a morphological image processor using VHDL - Part II: Control Mechanism
Author: Chen, Hao
Abstract: Very high speed integrated circuit Hardware Description Language (VHDL) is utilized in this project to model a Morphological Image Processor (MIP) Array. Both behavioral and structural models have been established at the system level, and the simulation results from both models are consistent with each other. The successful implementation of the models accomplishes our original goal to document the MIP with VHDL. It is observed from the project that VHDL is a powerful language. It is flexible since it can be used to model any level of a system independent of the technology.
Record URI: http://hdl.handle.net/1850/11744
Date: 1993-02

Files in this item

Files Size Format View
HChenThesis02-1993.pdf 9.282Mb PDF View/Open

The following license files are associated with this item:

This item appears in the following Collection(s)

Show full item record

Search RIT DML


Advanced Search

Browse