VHDL design of a DES encryption cracking system

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Title: VHDL design of a DES encryption cracking system
Author: Oelke, Thomas
Abstract: This thesis illustrates the design of a chip to crack a message encrypted with Digital Encryption Standard (DES). VHSIC Hardware Description Language (VHDL) is used to describe the system. Part of the design criteria of the system is to provide a scalable and reconfigurable set of DES building blocks in VHDL. In order to provide this, a modular design with a pipeline architecture is employed. This system could be synthesized to produce actual hardware in either an ASIC or FPGA part. Simulations using Synopsys with Actel's 3200DX FPGA library demonstrate that the design could be run at over 16Mhz. Because a pipelined architecture is employed which retires one key every clock cycle the chip would be able to test over 1 6 million keys per second. This is a vast improvement over current software-only based approaches that achieve speeds of 1 to 2 million keys per second on expensive high-end micro-processors.
Record URI: http://hdl.handle.net/1850/12767
Date: 1997-06

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