Modification of an asynchronous dexterous hand movement decoder for hardware implementation

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Title: Modification of an asynchronous dexterous hand movement decoder for hardware implementation
Author: Bosen, Adam Kevin
Abstract: One of the goals of modern prosthetics research is to provide natural, neurologically driven control of a prosthetic device, preferably in a portable format. Previously, an algorithm for asynchronously decoding individuated finger and wrist movements from recordings of neural activity in the primary motor cortex was developed by Aggarwal et al. and implemented in software. The first objective of this work was to determine what effect simplifying Aggarwal's algorithm by using linear Artificial neural networks instead of nonlinear ones would have on movement detection and classification accuracy. The simplified algorithm developed in this work was demonstrated to achieve movement detection and classification accuracies of 99.7%, 89.9%, and 95.3% for an individuated movement decoding task across three subjects using neural recordings from 80 neurons. In comparison, the original algorithm demonstrated accuracies of 96.2%, 90.5%, and 99.8% for the same task and subjects using neural recordings from 40 neurons. Additionally, the simplified algorithm was demonstrated to have a detection and classification accuracy of 80.5% for a combined movement task, whereas the original algorithm achieved accuracy of 92.5%. Even though a greater input space size was required for the linear decoder, the computational intensity was reduced with a mean accuracy loss in the individuated movement task of only 0.53%. However, the 12% loss of accuracy observed in the combined movement task is considered unacceptable and suggests that the simplified algorithm is not appropriate for this task. The second objective of this work was to create a digital hardware implementation of the simplified linear artificial neural network version of Aggarwal's algorithm. A scalable, fully parallel architecture was designed for implementation on a Xilinx Virtex-4 FX60 FPGA. This implementation could be realized with an input dimension of up to 60 neurons on this FPGA, although computations were performed on the order of 10<super>4</super> times faster than was necessary for realtime operation, indicating that there is an opportunity to reduce hardware size in exchange for computational speed. This work is an important exploration into the eventual goal of incorporating a hardware movement decoder in a prosthetic device and demonstrates that a hardware implementation is feasible using currently available technology.
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Date: 2010-06

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