ASIC design of an IIR digital filter: Using Mentor Graphics DSP Station Tools

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Title: ASIC design of an IIR digital filter: Using Mentor Graphics DSP Station Tools
Author: Panek, Robert
Abstract: Automation in VLSI design is a powerful way to simplify the VLSI layout process and will allow for faster time to market for integrated circuit designs. One means of automation is VHDL, a hardware description language for integrated circuit designs. A structured VHDL description can be used to describe the hardware design at the logic-gate level, and automated software is available that will use this gate-level design to generate the VLSI layout. A more recent type of automation occurs at a level above this. The Mentor Graphics DSP Station tools use a high-level algorithmic description to generate the gate-level VHDL description. These tools are especially intended for applications in digital signal processing (DSP), providing simulation tools particularly geared toward DSP algorithms. One application of digital signal processing is an infinite impulse response (IIR) filter. With the use of the Mentor Graphics tools, a digital filter was designed from a set of original specifications down to the silicon level. N-well 1.2 micron CMOS technology with two metal layers and one polysilicon layer was used to implement the filter layout. Using the 1.2 micron CMOSN standard cell library, the final VLSI layout measured 7.315 mm x 7.213 mm, containing approximately 25,700 transistors.
Record URI: http://hdl.handle.net/1850/13378
Date: 1995-05-01

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