Boundary scan system design

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Title: Boundary scan system design
Author: Loomis, Craig
Abstract: Given the strong competition in digital design on the national and international levels, boundary scan devices are rapidly becoming a necessary as opposed to a convenient feature on integrated circuits. This thesis serves a dual purpose. First, it demonstrates how boundary scan devices can be used to increase the testability of a circuit and it presents several factors used to quantify the cost associated with the addition of boundary scan compatibility to digital designs. Cost tradeoffs are often the most intimidating hurdle for engineers to cross when deciding if boundary scan compatibility is worth the effort. Second, it demonstrates the use of the Tektronix LV500 (logic verifier) as a general testing tool, using boundary scan designs as examples. These examples provide an understanding of the function of boundary scan cells and the JTAG/1 149. 1 standard. The LV500, which is used by students in the Department of Computer Engineering and Microelectronic Engineering at RIT, is an indispensable tool for making critical timing measurements. It also allows a user to evaluate and step through simple as well as more complicated designs. It is my hope that this thesis and the tutorial provided will facilitate the use of the LV500 in future testing work performed in RIT's center for Microelectronic and Computer Engineering clean room facilities. Upon following the example circuits described, one should become familiar with boundary scan terminology as well as the methodology used in designing such a system.
Record URI: http://hdl.handle.net/1850/13387
Date: 1996-06-17

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