Hardware Implementation of JPEG-LS codec

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Title: Hardware Implementation of JPEG-LS codec
Author: Piorun, Michael
Abstract: The primary goal of this thesis is to implement a hardware version of the JPEG-LS, or JPEGLossless, image compression algorithm in VHDL. The JPEG-LS algorithm is currently the designated standard for lossless compression of grayscale and color images by the JPEG committee. Although lossy image compression is widely used when dealing with grayscale images, there are some applications that require lossless image compression so that the original image may be recovered. This is often the case for historical and legal document image archives, medical and satellite imagery, and biometric images. The JPEG-LS algorithm is much less complex than other current lossless image compression algorithms and offers similar or better compression gains. Near-lossless compression offers higher compression gains by using a pixel tolerance specified by the user. The algorithm uses a predictive technique for compression, and the resulting prediction error is encoded, not the pixel value itself. This prediction error is encoded with Golomb-Rice coding, which is optimal for a geometric distribution such as prediction error. The predictor enters a special run-length mode to encode pixels with identical values in lossless mode (or nearly identical values within a known value in near-lossless mode), which maximizes compression further. In this thesis, the JPEG-LS algorithm is implemented in C, VHDL, and further synthesized using the Synopsys synthesis tool suite. Pictorial, document, medical, remote sensing, and biometric images are used for testing the project against another standard-compliant software implementation. The compression ratio for lossless compression is approximately 2 and is greater for near-lossless compression. The end result is a Synopsys schematic that represents a JPEG-LS codec, which is capable of lossless and near-lossless encoding and decoding. Performance characteristics such as chip area, speed, and power consumption are extracted from the synthesis tool. These are approximately 375,000 gates, a 15 ns clock cycle, and 59 mW respectively. A hardware implementation of this algorithm on an FPGA or ASIC would give a digital camera or scanner an edge in the marketplace.
Record URI: http://hdl.handle.net/1850/14117
Date: 2001-09

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