Development and evaluation of an intrinsic gettering process for fabrication of integrated circuits

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Title: Development and evaluation of an intrinsic gettering process for fabrication of integrated circuits
Author: Will, James ii
Abstract: An internal gettering process to collect and trap potentially harmful defects in the bulk of the silicon wafer, away from the surface where the integrated circuits are fabricated, has been developed in this work. This gettering process was then incorporated into the standard metal gate PMOS process utilized at RIT. Capacitors and diodes were electrically characterized to compare wafers that were gettered versus wafers that were not gettered. Results show that gettering did improve device characteristics, but only in the center of the wafers. The experimental results indicate that the diffusion of impurities from the furnace tube and quartz boat is competing with the gettering process during the lengthy furnace times. As a result, devices near the perimeter of the wafer exhibit poorer electrical characteristics after gettering when compared with the standards. This work shows that gettering will improve device performance, but only when accompanied by attention to furnace contamination. Gettering alone will not guarantee a better device.
Record URI: http://hdl.handle.net/1850/14492
Date: 2000-07

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