Analysis of H/W & S/W techniques for data reduction in high speed digital image processing

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dc.contributor.advisor Czernikowski, Roy
dc.contributor.advisor Sniatala, Pawel DeSanctis, Paul 2011-12-14T21:48:11Z 2011-12-14T21:48:11Z 2002-05-01
dc.description.abstract With the widespread utilization of charge-coupled-devices, there is much interest in methods to efficiently process images. The processing, manipulation, and storage of photographic quality digital images place significant demands on today's computers. Even with today's high performance bus structure and real-time operating systems, manipulating full resolution image data may quickly overwhelm computer hardware and software. In response to this, data reduction techniques have been developed to aid in resolving this problem. Two common data reduction techniques include data sub-sampling and data averaging. Data sub-sampling approach is simplistic in nature and perhaps easiest to implement in both hardware and/or software. This approach involves sub-sampling the full resolution image data to a lower resolution. Selection of sub-sampled element of the full resolution image is random in nature. This random selection makes sub-sampling an effective technique for flat image fields but degrades or softens the image for edges information quality/content. Data averaging approach is more difficult and complex to implement in both hardware and software than the sub-sampling approach. The data averaging approach involves a two dimensional averaging function to sub-sample the full resolution image data to a lower resolution. Averaging area parameters may be chosen to average X consecutive pixels, and Y consecutive lines. Although more complex, data averaging more effectively retains edge information. This thesis investigates the two-dimensional, pixel data-averaging method for data reduction. It supports the use of a pixel-averaging algorithm in conjunction with, or independent from compression techniques which may be employed elsewhere within the same system. Hardware and software implementations are presented to solve this system problem. The hardware architecture design is based on a pixel averaging application specific integrated circuit. Software routines written in C programming language are presented to perform this data-averaging task. Performance comparisons are made between the hardware and software implementations for image resolutions up to 2048 by 3072 pixels, and under several averaging conditions. This thesis also provides a survey of various types of charge-coupled devices sensors, focusing on their abilities and limitations for data averaging. It presents several applications where this type of data reduction would be advantageous. en_US
dc.language.iso en_US en_US
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dc.subject Computer engineering en_US
dc.subject Data storage en_US
dc.subject Efficient processing en_US
dc.subject Hardware en_US
dc.subject Image processing en_US
dc.subject Software en_US
dc.subject.lcc TA1637 .D47 2002
dc.subject.lcsh Image processing--Digital techniques en_US
dc.subject.lcsh Data reduction--Computer programs en_US
dc.title Analysis of H/W & S/W techniques for data reduction in high speed digital image processing en_US
dc.type Thesis en_US Kate Gleason College of Engineering en_US
dc.description.department Department of Computer Engineering en_US
dc.contributor.advisorChair Shaaban, Muhammad

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