A VHDL design for hardware assistance of fractal image compression

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Title: A VHDL design for hardware assistance of fractal image compression
Author: Erickson, Andrew
Abstract: Fractal image compression schemes have several unusual and useful attributes, including resolution independence, high compression ratios, good image quality, and rapid decompression. Despite this, one major difficulty has prevented their widespread adoption: the extremely high computational complexity of compression. Fractal image compression algorithms represent an image as a series of contractive transformations, each of which maps a large domain block to a smaller range block. Given only this set of transformations, it is possible to reconstruct an approximation of the original image by iteratively applying the transformations to an arbitrary image. Compression consists of partitioning the image into range blocks and finding a suitable transformation of a domain block to represent each one. This search for transformations must generally be done using a brute force approach, comparing successive domain blocks until a suitable match is found. Some algorithmic improvements have been found, but none are adequate to reduce the required compression time to something reasonable for many uses. This thesis presents a new ASIC design which performs a large number of the required comparisons in parallel, yielding a substantial speedup over a program on a general-purpose computer system. This ASIC is designed in VHDL, which may be synthesized to many different target architectures. The design has considerable flexibility which makes it applicable to different images and applications. The design is based around a pipeline of units that each compare one range block with a series of domain blocks which are fed through the pipeline. Comparisons are made to minimize the mean square error (MSE) of a transform given a linear mapping of the intensity values. This is, by far, the most common minimization strategy used in the literature. The speedup provided by this design is estimated to be about 1,000 times for 256 x 256 images divided into 8x8 blocks over a sequential processor given similar implementation technologies.
Record URI: http://hdl.handle.net/1850/14520
Date: 2000-06

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