Design of RIT's sub-micron CMOS process

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Title: Design of RIT's sub-micron CMOS process
Author: Bhaskaran, Suraj
Abstract: The design and simulation of RIT's sub-micron CMOS process is studied in this work. The work has demonstrated a process capable of producing working transistors with a channel length of 0.5um. New advancements such as dual well, low doped drain (LDD) regions and self-aligned silicides are a few mentioned highlights. The devices will be fabricated on 6" wafers using equipment recently donated to the RIT Microelectronic Engineering cleanroom facility. This calls for characterization of the new processes and equipment for optimized results. Device simulation was performed using MicroTec 2D Process/Device simulator from Siborg Systems. Simulated threshold voltage for the NFET device was on target, whereas the PFET transistors will require further process improvement.
Record URI: http://hdl.handle.net/1850/14610
Date: 2000-07-06

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