Analysis and hardware implementation of color map inversion algorithms

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Title: Analysis and hardware implementation of color map inversion algorithms
Author: Martin, Michael
Abstract: The purpose of this thesis is to investigate several algorithms that are used to compute the inverse of a forward printer map. The forward printer map models the printer by mapping points in the printer's input color space to points in the printer's output color space. The inverse of this forward map is required to convert input color specifications in a device-independent color space to a color in the printer's device-dependent color space before being presented to the print engine. The accuracy of the inverse printer map directly affects the accuracy of the reproduced colors. Therefore, any measured change in the forward printer map requires re-computation of the inverse map if accurate and consistent color reproduction is to be maintained. An efficient and accurate method of computing the inverse map could be used in an automatic color correction system. Three algorithms for computing the inverse of the forward printer map are studied in this thesis project. These are the Shepard's, Moving Matrix, and Iteratively Clustered Interpolation (ICI) algorithms. The algorithms are implemented in C and simulated in order to benchmark their relative accuracy, speed, and complexity. The simulations show the ICI algorithm to be the fastest and most accurate at computing the inverse map, and its complexity does not far exceed that of the other algorithms. The ICI algorithm was implemented in VHDL and synthesized to a Synopsys generic library in order to determine the approximate size and speed of an ASIC that could perform the inverse computation. The final implementation resulted in two modules: one that implements the ICI algorithm, and one that implements the trilinear interpolation function that is used by the ICI algorithm. The synthesized ICI module contained 112,683 cells, and the synthesized trilinear interpolation module contained 190,357 cells. The timing of the modules resulted in a 40 nanosecond clock period, which corresponds to a maximum operating frequency of 25 MHz. These synthesized results show that this algorithm is suitable for an ASIC that could be used in a real-time automatic color correction system.
Record URI: http://hdl.handle.net/1850/14872
Date: 2002-08

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