Ripple clock schemes for quantum-dot cellular automata circuits

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Title: Ripple clock schemes for quantum-dot cellular automata circuits
Author: Purohit, Prafull
Abstract: Quantum-dot cellular automata (QCA) is an emerging technology for building digital circuits at nano-scale. It is considered as an alternative to widely used complementary metal oxide semiconductor (CMOS) technology because of its key features, which include low power operation, high density and high operating frequency. Unlike conventional logic circuits in which information is transferred by electrical current, QCA operates with the help of coulomb interaction between two adjacent QCA cells. A QCA cell is a set of four quantum-dots that are placed near the corners of a square. Due to the fact that clocking provides power and control of data flow in QCA, it is considered to be the backbone of QCA operation. This thesis presents the design and simulation of a ripple clock scheme and an enhanced ripple clock scheme for QCA circuits. In the past, different clock schemes were proposed and studied which were focused on data flow in particular direction or reducing delay. This proposed thesis will study the design and simulation of new clock schemes which are more realistic for implementation, give a freedom to propagate logic in all directions, suitable for both combinational and sequential circuits and has potential to support testing and reconfiguration up to some extent. A variety of digital circuits including a 2–to–1 multiplexer, a 1–bit memory, an RS latch, a full adder, a 4–bit adder and a 2–to–4 decoder are implemented and simulated using these clock schemes. A 2–to–4 decoder is used to demonstrate the testing capabilities of these clock schemes. All QCA layouts are drawn and simulated in QCADesigner.
Record URI: http://hdl.handle.net/1850/15413
Date: 2012-05

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