0.18 µm CMOS low power standard cell library

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Title: 0.18 µm CMOS low power standard cell library
Author: Gunawan, Suryadi
Abstract: With the increasing number of transistors in a single integrated circuit, power is becoming one of the major issues in integrated circuit development. This issue requires additional effort from designers in order to produce lower power designs. The purpose of this thesis is to develop a standard cell library using Taiwan Semiconductor Manufacturing Company's 0.18-micron CMOS technology. The library cells consume less power compared to the vendor library provided by MOSIS. Although a reduction in power consumption is the main objective in this cell library, the timing delay and area are two aspects that cannot be ignored. However, a sacrifice has to be made in timing delay or area in order to achieve the goal of lower power. In order to produce a library that contains low power cells, a new design technique must be used while keeping in mind that power reduction should not adversely affect other aspects of the cell. Drawbacks in previously published design techniques will be analyzed and a new design technique composed of parts of previous techniques will then be postulated. The new technique will then be compared against the best technique currently available. A design technique for standard cell library development can be determined based on the results of that comparison. The new design technique can then be implemented into a cell library. The cell library is developed and characterized using Mentor Graphic tools. The newly produced cell library will then be compared to a similar technique used by the vendor library, determining that the produced cells consume lower amounts of power. Each cell will then be characterized by timing delay, area, truth tables, dimensions, and input capacitance.
Record URI: http://hdl.handle.net/1850/15461
Date: 2003-10-01

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