0.18μm high performance CMOS process optimization

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Title: 0.18μm high performance CMOS process optimization
Author: Gurcan, Zeki
Abstract: Complementary metal oxide semiconductor (CMOS) is the most widely used discrete structure in the semiconductor sector. Low static power consumption, full-rail high/low voltage transfer characteristics as well as its ease of scaling creates the perfect combination for the high performance integrated circuits (IC). Today’s challenging semiconductor industry profile brings the deadlines earlier than expected as a result of the shorter time-to- market plans as well as limited lifetime on sophisticated ICs. Process optimization for manufacturability is one of the most challenging issues in the semiconductor industry since the adoption of the sub-micron CMOS technology. Process technologies often times gets released with- in tight project schedules without jeopardizing the quality and customer’s trust. Manufacturing facilities often times institute very strict process controls in order to achieve the quality and the high yields. At the same time they take the financial burden of throwing away the nonconforming material which does not meet the ir specifications. Improving the device performance becomes the responsibility of the Integration/Device engineering through a series of process characterization studies. This paper outlines the various 0.18 μm. CMOS technology issues such as threshold voltage and saturation current control, and proposes methods to optimize the process through a series of characterization studies. 6-Sigma-DMAIC process was explored in order to achieve the desired goal. Techniques described in this thesis could be used in any manufacturing or development environment.
Record URI: http://hdl.handle.net/1850/5197
Date: 2005-07

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