0.18μm high performance CMOS process optimization

Show simple item record

dc.contributor.advisor Hirschman, Karl en_US
dc.contributor.advisor Fearon, Paul en_US
dc.contributor.advisor Kurinec, Santosh
dc.contributor.author Gurcan, Zeki en_US
dc.date.accessioned 2007-11-08T18:58:22Z en_US
dc.date.available 2007-11-08T18:58:22Z en_US
dc.date.issued 2005-07 en_US
dc.identifier.uri http://hdl.handle.net/1850/5197 en_US
dc.description.abstract Complementary metal oxide semiconductor (CMOS) is the most widely used discrete structure in the semiconductor sector. Low static power consumption, full-rail high/low voltage transfer characteristics as well as its ease of scaling creates the perfect combination for the high performance integrated circuits (IC). Today’s challenging semiconductor industry profile brings the deadlines earlier than expected as a result of the shorter time-to- market plans as well as limited lifetime on sophisticated ICs. Process optimization for manufacturability is one of the most challenging issues in the semiconductor industry since the adoption of the sub-micron CMOS technology. Process technologies often times gets released with- in tight project schedules without jeopardizing the quality and customer’s trust. Manufacturing facilities often times institute very strict process controls in order to achieve the quality and the high yields. At the same time they take the financial burden of throwing away the nonconforming material which does not meet the ir specifications. Improving the device performance becomes the responsibility of the Integration/Device engineering through a series of process characterization studies. This paper outlines the various 0.18 μm. CMOS technology issues such as threshold voltage and saturation current control, and proposes methods to optimize the process through a series of characterization studies. 6-Sigma-DMAIC process was explored in order to achieve the desired goal. Techniques described in this thesis could be used in any manufacturing or development environment. en_US
dc.format.medium Hardbound en_US
dc.language.iso en_US en_US
dc.rights I, Zeki B. Gurcan, hereby grant permission to the Wallace Memorial Library of the Rochester Institute of Technology to reproduce this document in whole or in part that any reproduction will not be for commercial use or profit. en_US
dc.subject Metal oxide semiconductors, Complementary en_US
dc.subject Design and construction en_US
dc.subject Metal oxide semiconductors en_US
dc.subject Reliability en_US
dc.subject.lcc TK7871.99.M44 G87 2005 en_US
dc.subject.lcsh Metal oxide semiconductors, Complementary--Design and construction en_US
dc.subject.lcsh Metal oxide semiconductors, Complementary--Reliability en_US
dc.title 0.18μm high performance CMOS process optimization en_US
dc.type Thesis en_US
dc.description.college College of Engineering en_US
dc.description.department Department of Microelectronic Engineering en_US
dc.contributor.advisorChair Fuller, Lynn

Files in this item

Files Size Format View
2005_Zeki_Gurcan.pdf 2.772Mb PDF View/Open

This item appears in the following Collection(s)

Show simple item record

Search RIT DML


Advanced Search

Browse