On-chip probe metrology

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Title: On-chip probe metrology
Author: Farner, William Robert
Abstract: The semiconductor market was valued at over $270 billion in 2007, with projections to continue steady growth [7]. Any manufacturing process of this volume is tightly controlled to ensure high efficiency, and improvements are readily sought after. Despite semiconductor fabrication process advancements allowing circuits to contain larger numbers of transistors in smaller package sizes, there has not been any significant change in the way these circuits interface with test systems before packaging. This limitation causes the area overhead occupied by circuit contacts, known as bond pads, to become increasingly costly. To amend the situation, VLSI designers have attempted to reduce bond pads size and pitch as much as possible while retaining reliable probing accuracy [15]. Currently, there is no standard solution to assess the accuracy of probe stations inline with wafer testing. As such, a balance must be struck between overhead cost of large bond pads and operational cost spent analyzing probe performance off-line. A feedback loop on probe card performance during wafer fabrication sort could allow plants to recalibrate probe cards before a yield drop is detected, thus improving yield and saving operational costs [26]. This thesis demonstrates a proof of concept design that offers a viable solution to perform probe metrology in-line with wafer-level circuit testing. A versatile circuit was designed and laid out that promises fine accuracy resolution of 3.21 μm, and fast test time of 1.25 ms per probe.
Record URI: http://hdl.handle.net/1850/6207
Date: 2008-05

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