Teaching pipelining and concurrency using hardware description languages

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Title: Teaching pipelining and concurrency using hardware description languages
Author: Melton, Roy; Huang, Tsai; Yalamanchili, Sudhakar; Bighman, Philip; Alford, Cecil
Abstract: Relating to a previous simplified VHDL processor model [1], a more advanced synthesized VHDL pipeline microprocessor model was developed and has been used in the second term computer architecture course offered in the School of Electrical and Computer Engineering at the Georgia Institute of Techonology. This paper will first describe the pipeline processor model and its VHDL implementation. Then, it presents various implementation extensions that have been assigned and completed within a satisfactory period by participating students.
Description: Proceedings 1999 IEEE International Conference on Microelectronic Systems Education, Las Vegas, Nevada: June28-July 1, 1999.
Record URI: http://hdl.handle.net/1850/7253
Date: 1999-07

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