A Novel 5.46 mW H.264/AVC video stream parser IC

Show full item record

Title: A Novel 5.46 mW H.264/AVC video stream parser IC
Author: Brown, Michelle; Hsu, Kenneth
Abstract: This paper presents a 5.46 mW H.264/AVC Video Stream Parser implemented in 65nm. The differences between targeting a video stream parser architecture for a 65nm CMOS ASIC and a Virtex 5 FPGA are also compared. Overall, the ASIC implementations showed higher performance and lower area than an FPGA, with a 600/0 increase in performance and 6x decrease in area.
Description: This paper appears in: SOC Conference, 2008 IEEE International.
Record URI: http://hdl.handle.net/1850/8703
Date: 2008-09

Files in this item

Files Size Format View
KHsuConfProc09-2008.pdf 1.535Mb PDF View/Open

The following license files are associated with this item:

This item appears in the following Collection(s)

Show full item record

Search RIT DML


Advanced Search

Browse