Three dimensional multi-valued design in nanoscale integrated circuits

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Title: Three dimensional multi-valued design in nanoscale integrated circuits
Author: Lyshevski, Sergey
Abstract: Novel three-dimensional (3D) nanoscale integrated circuits (nanoICs) are examined in this paper. These nanoICs are synthesized utilizing aggregated 3D neuronal-hypercells (ℵ-hypercells) with multi-terminal electronic nanodevices. The proposed nanodevices ensure multi-valued input-output characteristic that lead to a direct technological solution of multi-valued logic synthesis problem. Super-high-performance computing architectures and memories can be devised (synthesized), designed and optimized. At the system-level, we examine nanoICs as networked aggregated 3D ℵ-hypercells. In particular, scalable 3D ℵ-hypercell topologies are under consideration. These ℵ-hypercells integrate interconnected functional multi-terminal electronic nanodevices that implement logic functions. The proposed nanoICs platform suits the envisioned cognizant computing ensuring preeminent information processing and immense memory.
Description: Copyright 2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.Proceedings of the 35th International Symposium on Multiple-Valued Logic (ISMVL’05)
Record URI: http://hdl.handle.net/1850/8897
Date: 2005-05

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