A Microprocessor based hybrid system for digital error correction

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dc.contributor.advisor Rhody, Harry
dc.contributor.advisor Riethaman, Alton
dc.contributor.advisor Hsu, Kenneth
dc.contributor.advisor Seminkowski, Ray
dc.contributor.author Sohn, Peter H.
dc.date.accessioned 2009-06-17T19:11:17Z
dc.date.available 2009-06-17T19:11:17Z
dc.date.issued 1984-06
dc.identifier.uri http://hdl.handle.net/1850/9861
dc.description.abstract The design of a microprocessor based hybrid system for digital error correction is presented. It is shown that such a system allows for implementation of several cyclic codes at a variety of throughput rates providing variable degrees of error correction depending on current user requirements. The theoretical basis for encoding and decoding of binary BCH codes is reviewed. Design and implementation of system hardware and software are described. A method for injection of independent bit errors with controllable statistics into the system is developed, and its accuracy verified by computer simulation. This method of controllable error injection is used to test performance of the designed system. In analysis, these results demonstrate the flexibility of operation provided by the hybrid nature of the system. Finally, potential applications and modifications are presented to reinforce the wide applicability of the system described in this thesis. en_US
dc.language.iso en_US en_US
dc.subject Error correction en_US
dc.subject Hybrid system en_US
dc.subject System design en_US
dc.subject.lcc QA76.9.S88 S68 1984
dc.subject.lcsh System design en_US
dc.subject.lcsh Error-correcting codes (Information theory) en_US
dc.title A Microprocessor based hybrid system for digital error correction en_US
dc.type Thesis en_US
dc.description.college Kate Gleason College of Engineering en_US
dc.description.department Department of Electrical Engineering en_US

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