A QCA implementation of a configurable logic block for an FPGA

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dc.contributor.author Lantz, Timothy
dc.contributor.author Peskin, Eric
dc.date.accessioned 2009-06-17T19:12:20Z
dc.date.available 2009-06-17T19:12:20Z
dc.date.issued 2006-09
dc.identifier.isbn 1-4244-0690-0
dc.identifier.uri http://hdl.handle.net/1850/9864
dc.description Proceedings from the 2006 IEEE reconfigurable computing and FPGA's international conference. Copyright 2006 IEEE. en_US
dc.description.abstract This paper presents the design, layout, and successful simulation of a configurable logic block (CLB) for a field-programmable gate array (FPGA) architecture based on a next-generation technology, quantum-dot cellular automata (QCA). Previous work on QCA-based FPGAs has focused on programmable interconnect. In contrast, this paper focuses on programmable logic. A novel single-layer CLB with fixed interconnect is developed by implementing four look-up tables (LUTs). Also, this paper presents a novel serial write/random-access read QCA memory design, which is one of the components in a LUT QCADesigner software is used to design and simulate a 4-to-16 decoder, 16-bit memory, and output circuit to implement a LUT. The simulation of the CLB confirms the expected outcomes en_US
dc.language.iso en_US en_US
dc.publisher IEEE en_US
dc.subject Cellular automata en_US
dc.subject Field programmable gate arrays en_US
dc.subject Quantum dots en_US
dc.title A QCA implementation of a configurable logic block for an FPGA en_US
dc.type Proceedings en_US

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