Development, fabrication, and characterization of a vertical-diffused MOS process for power RF applications

Show full item record

Redirect: RIT Scholars content from RIT Digital Media Library has moved from to RIT Scholar Works, please update your feeds & links!
Title: Development, fabrication, and characterization of a vertical-diffused MOS process for power RF applications
Author: Tokunaga, Kazuya
Abstract: High power radio frequency (RF) applications have become important because of a growing demand from the wireless market. With their superior switching speed, power Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) have become one of the well-known technologies used in high power RF systems. The primary focus of this thesis work was the development, fabrication, and characterization of discrete Verticaldrain lateral-Diffused MOS (VDMOS) power transistors using an interdigitated source/gate design. Several types of high power devices were also presented for comparison to the VDMOS structure. This thesis describes the overall purpose and the objectives of the proposed project, and provides the methodology used to complete these objectives. This project supports a new development initiative of the project sponsor, Spectrum Devices, Inc., who has been working with RIT in power bipolar technologies over the last two years. The process steps to create a 50 V power VDMOS transistor structure were designed using Silvaco ATHENA (SUPREM-IV) process simulation. Typical power VDMOS transistor fabrication steps were used as a starting point with modifications to include Faraday and UIS implant steps to address certain parasitic effects. The Faraday shield implant was performed to shift the parasitic gate- field capacitance over to the input side of the device, which should dramatically improve the frequency response of the device. The UIS implant was used to reduce the parasitic BJT of a power VDMOS transistor. The implementation of the proposed structure also eliminated the need for an added masking operation for each implant step, and kept the structure self- aligned to the gate stack. This eliminated potential overlay tolerances and error that may be encountered in photolithography steps. The initial process parameters were carefully varied and adjusted to meet the target specifications (such as threshold voltage, breakdown voltage, gate oxide thickness, etc.) using ATHENA and ATLAS simulation software. After the device fabrication was completed, DC testing was performed on the fabricated VDMOS transistors both at RIT and at Spectrum Devices. A successful extraction of the transfer curves, family of curves, and breakdown voltage plots both in low and high current settings was achieved. The designed process produced a power VDMOS with a breakdown voltage of up to 180 V, a threshold voltage of ~3.8 V, a transconductance up to ~7 mhos, and an operating current of nearly 5 A. The experimental results were compared to the target specification provided by Spectrum Devices. In addition, impacts of the Faraday shield implant on the breakdown voltage and terminal capacitances of a VDMOS device were verified through DC testing. Preliminary wafer- level AC testing was performed and demonstrated the functional performance of the device up to 100 kHz frequency range. Although it would be interesting to see the impact of UIS implant step on a device performance, no AC test was yet to be performed. This work presented the first power VDMOS transistors successfully fabricated and characterized at RIT. With the data and information obtained from this thesis project, process modifications and adjustments should yield devices with improved performance.
Record URI:
Date: 2008-12

Files in this item

Files Size Format View
KTokunagaThesis12-2008.pdf 11.59Mb PDF View/Open

The following license files are associated with this item:

This item appears in the following Collection(s)

Show full item record

Search RIT DML

Advanced Search